Semiconductor flash memory devices include NAND-type flash memory devices. Such memory devices typically comprise a high density core region and a low density peripheral region on a single substrate. The memory cells within the core region are coupled together in a NAND-type circuit configuration, as illustrated in FIGS. 1A and 1B. FIG. 1A illustrates a circuit schematic diagram of the core region 11 while FIG. 1B illustrates a plan view of the core region 11. The core region 11 includes a memory cell region 22 which is bounded on one side by a drain select transistor portion 24 and bounded on another side by a source select transistor portion 26. Each of the select transistor portions 24 and 26 contain select gate transistors 24a-24c and 26a-26c, respectively, which operate to selectively activate a desired bit line.
FIG. 1C illustrates a cross-section of conventional stack structures of a select transistor 100 and a memory cell 150 in the core region 11. The stack structure 150 of the memory cell includes a tunnel oxide 104 on a substrate 102 and a floating gate 106 composed of polysilicon on the tunnel oxide 104. The control gate comprises a polysilicon layer 110 and a tungsten silicide layer 112 on the polysilicon layer 110. A dielectric layer insulates the floating gate 106 from the control gate 110 and 112. The control gate 110 and 112 is coupled to a word line. A cap layer 114 composed of silicon oxynitride resides on the control gate 110 and 112 and provides an anti-reflective coating at masking.
The stack structure 100 of the select transistor comprises a select gate oxide 116 on the substrate 102. A select gate 118 is on the select gate oxide 116. Like the memory cell stack structure 150, the control gate of the select transistor includes a polysilicon layer 122 and a tungsten silicide layer 124. A dielectric layer 120 insulates the select gate 118 from the control gate 122 and 124. The stack structure 100 is topped by a silicon oxynitride layer 126.
Typically, the floating gate 106 of the memory cell stack structure 150 and the select gate 118 of the select transistor stack structure 100 are formed from a single in-situ doped polysilicon layer. Subsequent masking and etching provides the resulting floating gate 106 and the select gate 118. In order to properly perform the programming and erasure of the memory cell, this single polysilicon layer must be conductive. It may be rendered conductive by using doped amorphous silicon for the single polysilicon layer. The dopant level of the single polysilicon layer is critical in the performance of the memory cell and thus the semiconductor device as a whole.
However, there are two conflicting factors in determining the level of dopant for the single polysilicon layer. If the dopant level is too low, this will cause the control gate contact resistance of the select transistor to become too high since the select gate 118 is connected to the control gate 122 and 124 via an interconnect (not shown). This causes the select transistor word line resistance to also become too high, resulting in a slower circuit performance. If the dopant level is too high, some of the dopant will contaminate the tunnel oxide 104 of the memory cell, which causes the surface of the floating gate 106 and tunnel oxide 104 interface to be rough. The rough interface leads to a high local electric field and a lower oxide dielectric strength. This causes reliability problems and a charge gain/loss problem in the programming and erasure of the memory cell.
Accordingly, there exists a need for a method and NAND-type flash memory device for providing a polysilicon dopant level which avoids both the select transistor word line high resistance and the charge gain/loss problems. The present invention addresses such a need.